The present invention relates to bumps formed on connection terminals of a semiconductor substrate for mounting a semiconductor device such as a semiconductor IC, and a method of manufacturing the bumps.
In recent years, as portable electronic equipment such as a digital video camera, a digital portable telephone, or a notebook type personal computer has been widespread, there has been a strong demand toward miniaturization, thinning and lightweightness of the portable electronic equipment.
To realize the miniaturization, thinning and lightweightness of the portable electronic equipment, it is important to improve the mounting density of parts.
In particular, with respect to a semiconductor device such as a semiconductor IC, a high density mounting technique using a flip-chip type semiconductor device has been developed and practically used in place of a conventional package type semiconductor device.
For example, mounting of such a flip-chip type semiconductor device (flip-chip mounting) is carried out by forming solder ball bumps on A1 electrode pads provided on a semiconductor IC, and bringing the solder ball bumps of the semiconductor IC in a chip state into contact with connection terminals of a printed circuit board, to thereby directly mount the IC chip on the printed circuit board.
The above solder ball bumps are manufactured by making use of an electroplating process. With this process, the thickness of a solder layer formed by electroplating is affected by the surface state of an underlying layer and a slight variation in electric resistance. This causes a problem that it is basically difficult to form solder ball bumps having uniform heights in one IC chip.
On the contrary, as a method of manufacturing solder ball bumps in such a manner as to suppress a variation in height of the solder ball bumps, there has been known a method of forming a pattern of solder ball bumps by making use of film formation due to vacuum vapor deposition and lift-off of a photoresist film.
The latter method will be described with reference to FIGS. 4A to 4E.
Referring first to FIG. 4A, an electrode portion 1a of a flip-chip type semiconductor IC 1 is formed as follows:
An electrode pad 3 typically made from an Al--Cu alloy is formed on a semiconductor substrate 2 typically made from silicon by sputtering, etching and the like. A surface protective film 4 typically made from silicon nitride or polyimide is formed over the entire surface of the semiconductor substrate 2 in such a manner as to cover the electrode pad 3. An opening 4a is formed in the surface protective film 4 at a region of the electrode pad 3. A metal multi-layer film 5 typically made from Cr, Cu, Au and the like, which is called a BLM (Ball Limiting Metal) film, is formed by typically sputtering in such a manner as to cover the surface of the electrode pad 3 exposed to the side surface and the bottom of the opening 4a. The electrode portion la is composed of these electrode pad 3, surface protective film 4, opening 4a, and BLM film 5.
To form a solder ball bump on the electrode portion 1a which is provided on the semiconductor IC 1 as described above, as shown in FIG. 4B, a resist film 6 having an opening 6a at a region of the BLM film 5 is formed.
Referring to FIG. 4C, a solder vapor deposition film 7 is formed on the entire surface of the semiconductor substrate 2 via the resist film 6.
Referring to FIG. 4D, the resist film 6 is lifted-off, to remove an unnecessary portion of the solder vapor deposition film 7, whereby the solder vapor deposition film having a specific pattern is formed.
Referring to FIG. 4E, the semiconductor substrate 2 is subjected to heat-treatment, to melt the solder of the solder vapor deposition film 7, whereby an approximately spherical solder ball bump 7a is formed due to the surface tension of the solder.
In general, the formation of the solder ball bumps 7a are performed for the semiconductor ICs 1 left as a semiconductor wafer state, that is, in the state before the semiconductor wafer is cut into the individual semiconductor ICs 1.
After the solder ball bumps 7a are formed on respective electrode portions 1a provided on the semiconductor ICs 1, the wafer-like semiconductor substrate 2 is cut into the individual chip-like semiconductor ICs 1 typically by dicing.
Referring to FIG. 5, the solder ball bumps 7a of each semiconductor IC 1 are brought into contact with lands 8a as connection portions typically made from Cu formed on a printed circuit board 8 to which the semiconductor IC 1 is to be mounted.
The surface of the printed circuit board 8 is covered with a solder resist 8b excluding the lands 8a, and regions of the lands 8a are pre-coated with an eutectic solder film 8c.
At a reflow step, the eutectic solder film 8c is melted. The melted eutectic solder permeates between the solder ball bumps 7a and the lands 8a, and cooled and hardened, whereby each ball bump 7a is soldered to the land 8a, that is, it is electrically connected thereto.
The above solder bonding between the solder ball bump 7a and the land 8a suffers thermal stress due to environmental temperature change because the thermal expansion coefficient of the semiconductor substrate 2 of the semiconductor IC 1 is different from that of the printed circuit board 8.
To be more specific, the thermal expansion coefficient of silicon forming the semiconductor substrate 2 is as small as 3.4 ppm/.degree. C., while the thermal expansion coefficient of a glass reinforced epoxy resin based substrate generally used as the printed circuit board 8 is as large as about 15 ppm/.degree. C. Accordingly, when thermal stress is repeatedly applied to the solder bonding portion between the solder ball bump 7a and the land 8a due to a temperature difference caused by on/off operation of the semiconductor IC 1, cracking may occur at the solder bonding portion, and at the worst case, the cracking leads to breakage, to cause electric disconnection at the solder bonding portion, thereby inducing a so-called breakage failure. That is to say, the above-described structure has a problem associated with the reliability of solder bonding.
To suppress breakage of the solder bonding portion due to thermal stress, there has been generally adopted a method in which a sealing resin 9 is injected between the semiconductor IC 1 and the printed circuit board 8 as shown in FIG. 5. In this method, the entire sealing resin 9 sustains the above-described thermal stress, to moderate the thermal stress applied to the solder bonding portion, thereby enhancing the strength against the thermal stress.
In the above method using the sealing resin 9, the semiconductor IC 1 is integrally fixed on the printed circuit board 8 by the sealing resin 9. Accordingly if the semiconductor IC 1 fails, the printed circuit board 8 on which the failed semiconductor IC 1 is mounted is exchanged as a whole, then discarded as a defective or the failed semiconductor IC 1 is forcibly peeled from the printed circuit board 8 by applying an external chemical or mechanical force thereto.
The former exchange of the printed circuit board 8 as a whole causes a problem in raising the cost while the latter forced peeling of the semiconductor IC 1 causes a problem in damaging the printed circuit board 8.
In this way, the method using the sealing resin 9 is disadvantageous in that if the semiconductor IC 1 fails, the exchange work, that is, the rework of the failed part cannot be easily performed. This is one reason why flip-chip mounting has been not widespread.
The method using the sealing resin 9 has another problem. With a tendency toward a so-called narrow pitch accompanied by miniaturization of a semiconductor device, the runabout of the sealing resin 9 having been injected between the semiconductor IC 1 and the printed circuit board 8 becomes poor, with a result that it is difficult to realize perfect injection of the sealing resin 9. The sealing resin 9 thus imperfectly injected fails to sufficiently moderate the thermal stress applied to the solder bonding portion.